1. Field of the Invention
The present invention relates to an arrangement for testing full-scan digital circuits more efficiently, in particular using conventional ATPG tools and techniques.
2. Description of the Related Art
The testing of digital circuits using scan chains is well known to those skilled in the art. In brief, a scan chain is a series of linked flip-flops which are arranged through areas of combinatorial logic on an integrated digital circuit. Each flip-flop receives an input from the previous flip-flop in the chain, and from the combinatorial logic through which the chain passes. At an input pin, a test pattern of logic 1's and 0's is input to the scan chain, and passes through the sequence of flip-flops and combinatorial logic to an output pin. The output sequence of logic 1's and 0's is changed from the input sequence by operation of the logic under test. The manner in which the sequence is changed is not important to determining whether the circuit is functioning correctly. The circuit can be determined to pass or fail the test by simply comparing the output sequence with the output sequence of a correctly functioning circuit.
ITC International Test Conference paper 0-7803-6546-1/00 “Using On-Chip Test Pattern Compression for Full Scan S&C Designs” Lang, Pfeiffer & Maguire proposes various improvements to testing using scan chains. A scan chain architecture is proposed which uses a multiple input shift register (MISR) to receive inputs from a plurality of scan chains to provide a single output, thereby reducing the number of output pins required.
It is standard practice A further improvement is to use software for automatic generation of the test sequences of logic 1's and 0's, known as test patterns, and perform analysis. Such tools are known as Automatic Test Pattern Generation (ATPG) tools and are integral to full scan testing increase the speed of chip testing. A known example is Tetramax™ of Synopsys, Inc. Whilst this tool enhances the speed of testing, on large chips the testing task is significant. On recent graphics chips designs there can be 170 scan chains with 2,600 flip-flops each. This results in excessive test vector counts and/or low test coverage a large processing burden.